ADI AD9511BCPZ

Fanout Буфер (распределение), делитель12:5

Overview

The PLL section consists of a programmable reference divider, R; a low-noise phase frequency detector, PFD; a precision charge pump, CP; and a programmable feedback divider, N. By connecting an external VCXO or VCO to the CLK2 and CLK2B pins, PLL output frequencies up to 1.6 GHz may be synchronized to the input reference, REFIN.

The AD9511BCPZ is available in a 48-lead LFCSP and is specified from -40°C to +85°C. The part may be run from a single 3.3 V supply. Users wishing to extend the voltage range for external VCOs may run the charge pump supply, VCP, to 5.5V.

Features

Applications

• Clock signal format conversion
• Clock signal level shifting
• High performance communication system
• Data center
• Cloud computing
• Network
• High speed industry
• High-end consumer electronics
• Data communication
• Telecommunications