ADI AD9528BCPZ-REEL7

Да с байпасомCMOS, HSTL, LVDSHSTL, LVDS

Overview

The AD9528BCPZ-REEL7 is a two-stage PLL with an integrated JESD204BSYSREF generator for multiple device synchronization. The firststage phase-locked loop (PLL) (PLL1) provides input referenceconditioning by reducing the jitter present on a system clock.The second stage PLL (PLL2) provides high frequency clocksthat achieve low integrated jitter as well as low broadband noisefrom the clock output drivers. The external VCXO provides thelow noise reference required by PLL2 to achieve the restrictivephase noise and jitter requirements necessary to achieve acceptableperformance. The on-chip VCO tunes from 3.450 GHz to4.025 GHz. The integrated SYSREF generator outputs singleshot, N-shot, or continuous signals synchronous to the PLL1and PLL2 outputs to time align multiple devices.

The AD9528BCPZ-REEL7 generates six outputs (Output 0 to Output 3,Output 12, and Output 13) with a maximum frequency of1.25 GHz, and eight outputs with a maximum frequency of upto 1 GHz. Each output can be configured to output directlyfrom PLL1, PLL2, or the internal SYSREF generator. Each of the14 output channels contains a divider with coarse digital phaseadjustment and an analog fine phase delay block that allowscomplete flexibility in timing alignment across all 14 outputs.The AD9528BCPZ-REEL7 can also be used as a dual input flexible buffer todistribute 14 device clock and/or SYSREF signals. At power-up,the AD9528BCPZ-REEL7 sends the VCXO signal directly to Output 12 andOutput 13 to serve as the power-up ready clocks.

Features

Applications

• Automatic test equipment
• Wide area power system
• Digital circuits
• Wireless base station for LTE, LTE-advanced
• Picocells, femtocells and small cells
• Sampling clocks for ADC and DAC
• 1 Gigabit Ethernet
• 10 Gigabit Ethernet
• FPGA and processor clocks
• Line cards used in telephone exchange