ADI AD9575ARUZLVD

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Overview

The PLL section consists of a low noise phase frequency detector (PFD), a precision charge pump, a low phase noise voltagecontrolled oscillator (VCO), and pin selectable feedback and output dividers. By connecting an external crystal, popular network output frequencies can be locked to the input reference. The output divider and feedback divider ratios are pin programmable for therequired output rates. No external loop filter components are required, thus conserving valuable design time and board space.

The AD9575ARUZLVD is available in a 16-lead, 4.4 mm × 5.0 mm TSSOP and can be operated from a single 3.3 V supply. The temperature range is −40°C to +85°C.

Features

Bulk Package
Mounting Type: Surface Mount
Peak Reflow Temperature (Cel): 260
uPs/uCs/Peripheral ICs Type of CLOCK GENERATOR, OTHER
Include 1 Circuits
run the output at th range of LVCMOS, LVDS, LVPECL
with 16 Pins
operate supply voltage at the range of 3.3V

3V ~ 3.6V Voltage - Supply

Applications

There are a lot of Analog Devices Inc.
AD9575ARUZLVD application specific timer applications.

• Processor and FPGA clocking
• Any-frequency clock conversion
• MSAN/DSLAM/PON
• Fibre Channel, SAN
• Telecom line cards
• 1 GbE and 10 GbE
• Servers, Storage, Search Acceleration
• Ethernet Switches, Routers
• Small Cells, Mobile Backhaul/Fronthaul
• Print Imaging