Altera EP4CE40F29C7N

396001161216532

Overview

This chapter describes the electrical and switching characteristics for Cyclone IV devices. Electrical characteristics include operating conditions and power consumption. Switching characteristics include transceiver specifications, core, and periphery performance. This chapter also describes I/O timing, including programmable I/O element (IOE) delay and programmable output buffer delay. This chapter includes the following sections: ■ “Operating Conditions” on page 1–1 ■ “Power Consumption” on page 1–16 ■ “Switching Characteristics” on page 1–16 ■ “I/O Timing” on page 1–37 ■ “Glossary” on page 1–37

DC Characteristics This section lists the I/O leakage current, pin capacitance, on-chip termination (OCT) tolerance, and bus hold specifications for Cyclone IV devices. Supply Current The device supply current requirement is the minimum current drawn from the power supply pins that can be used as a reference for power size planning. Use the Excel-based early power estimator (EPE) to get the supply current estimates for your design because these currents vary greatly with the resources used. 

Features

• Cyclone IV E—lowest power, high functionality with the lowest cost

• Cyclone IV GX—most insufficient power and lowest price FPGAs with 3.125 Gbps transceivers

• 6K to 150K logic elements

• Up to 6.3 Mb of embedded memory

• Up to 360 18 × 18 multipliers for DSP processing-intensive applications

• Protocol bridging applications for under 1.5 W total power

• Data rates up to 3.125 Gbps

• 8B/10B encoder/decoder

• 8-bit or 10-bit physical media attachment (PMA) to physical coding sublayer (PCS) interface

• Byte serializer/deserializer (SERDES)

• Word aligner

• Rate matching FIFO

• TX bit slipper for Common Public Radio Interface (CPRI)

• Electrical idle

• Dynamic channel reconfiguration allows you to change data rates and protocols on-the-fly

• Static equalization and pre-emphasis for superior signal integrity

• 150 mW per channel power consumption

• Flexible clocking structure to support multiple protocols in a single transceiver block

Applications

• Industrial