IDT 71V546S100PFG

128K x 365 нс0°C ~ 70°C (TA)

Overview

The 71V546S100PFG 3.3V CMOS SRAM is organized as 128K x 36 bits. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus it has been given the name ZBTTM, or Zero Bus Turn-around. The 71V546S100PFG contains data I/O, address and control signal registers. In the burst mode, it can provide four cycles of data for a single address presented to the SRAM.

Features

Applications

• telecommunications
• workstations,
• DVD disk buffer
• data buffer
• nonvolatile BIOS memory
• Camcorders
• embedded logic
• eDRAM
• graphics card
• hard disk drive (HDD)