Intel EPM9560RI208-20

Программируемый в системе20 нс35560153

Overview

The MAX 9000 family of in-system-programmable, high-density, highperformance EPLDs is based on Altera’s third-generation MAX architecture. Fabricated on an advanced CMOS technology, the EEPROMbased MAX 9000 family provides 6,000 to 12,000 usable gates, pin-to-pin delays as fast as 10 ns, and counter speeds of up to 144 MHz. The -10 speed grade of the MAX 9000 family is compliant with the PCI Local Bus Specification, Revision 2.2. Table 3 shows the speed grades available for MAX 9000 devices.

■ Offered in a variety of package options with 84 to 356 pins (see Table 2

Features

Applications

• Timing control
• Interface bridging
• I/O expansion
• Discrete logic functions
• Bootloaders for FPGAs
• Address decoders
• Custom state machines
• Digital systems
• Portable digital devices
• Handheld digital devices