Intersil CD74HCT273M

830нс @ 4,5В, 50пФ4,5 В ~ 5,5 В

Overview

Data sheet acquired from Harris Semiconductor

Information at the D inputis transferred to the Q outputs on the positive-going edge of the clock pulse. All eight flip-flops are controlled by a common clock (CP) and a common reset (MR). Resetting is accomplished by a low voltage level independent of the clock. All eight Q outputs are reset to a logic 0.

Features

Applications

• Shift Registers
• Storage Registers
• Bounce elimination switch
• Data storage
• Data transfer
• Latch
• Registers
• Memory
• Frequency division
• Memory