Intersil ISL85410AIRZ

Overview

The a 1A Synchronous buck regulator with an input range 36V. It provides an easy to use, high efficiency low BOM count solution for a variety of applications. The ISL85410FRZ integrates both high-side and low-side NMOS FET's and features a PFM mode for improved efficiency at light loads. This feature can be disabled if forced PWM mode is desired. The part switches at a default frequency of 500kHz but may also be programmed using an external resistor from to 2MHz. The ISL85410FRZ has the ability to utilize internal or external compensation. By integrating both NMOS devices and providing internal configuration options, minimal external components are required, reducing BOM count and complexity of design. With the wide VIN range and reduced BOM the part provides an easy to implement design solution for a variety of applications while giving superior performance. It will provide a very robust design for high voltage Industrial applications as well as an efficient solution for battery powered applications. The part is available in a small Pb free 4mmx3mm DFN plastic package with an operation temperature range to +125�C

PIN NUMBER 1 SYMBOL SS PIN DESCRIPTION The SS pin controls the soft-start ramp time of the output. A single capacitor from the SS pin to ground determines the output ramp rate. See "Soft Start" on page 14 for soft-start details. If the SS pin is tied to VCC, an internal soft-start of 2ms will be used. Synchronization and light load operational mode selection input. Connect to logic high or VCC for PWM mode. Connect to logic low or ground for PFM mode. Logic ground enables the IC to automatically choose PFM or PWM operation. Connect to an external clock source for synchronization with positive edge trigger. Sync source must be higher than the programmed IC frequency. There is an internal 5M pull-down resistor to prevent an undefined logic state if SYNC is left floating. Floating bootstrap supply pin for the power MOSFET gate driver. The bootstrap capacitor provides the necessary charge to turn on the internal N-Channel MOSFET. Connect an external 100nF capacitor from this pin to PHASE. The input supply for the power stage of the regulator and the source for the internal linear bias regulator. Place a minimum of 4.7�F ceramic capacitance from VIN to GND and close to the IC for decoupling. Switch node output. It connects the switching FET's with the external output inductor. Power ground connection. Connect directly to the system GND plane. Regulator enable input. The regulator and bias LDO are held off when the pin is pulled to ground. When the voltage on this pin rises above 1V, the chip is enabled. Connect this pin to VIN for automatic start-up. Do not connect EN pin to VCC since the LDO is controlled by EN voltage. Open drain power-good output that is pulled to ground when the output voltage is below regulation limits or during the soft-start interval. There is an internal 5M internal pull-up resistor. Output of the internal 5V linear bias regulator. Decouple to PGND with a 1�F ceramic capacitor at the pin. Feedback pin for the regulator. FB is the inverting input to the voltage loop error amplifier. COMP is the output of the error amplifier. The output voltage is set by an external resistor divider connected to FB. In addition, the PWM regulator's power-good and UVLO circuits use FB to monitor the regulator output voltage. COMP is the output of the error amplifier. When it is tied to VCC, internal compensation is used. When only an RC network is connected from COMP to GND, external compensation is used. See "Loop Compensation Design" on page 17 for more details. Frequency selection pin. Tie to VCC for 500kHz switching frequency. Connect a resistor to GND for adjustable frequency from to 2MHz. Signal ground connections. Connect to application board GND plane with at least 5 vias. All voltage levels are measured with respect to this pin. The EPAD MUST not float.

Features