Lattice OR3L225B7BM680-DB

8192134144516

Overview

■High-performance, cost-effective, 0.25 um 5-level metal technology.

■Fast-carry logic and routing to adjacent PFUs for nibble-wide, byte-wide, or longer arithmetic functions, with the option to register the PFU carry-out. ■Softwired LUTs (SWL) allow fast cascading of up to three levels of LUT logic in a single PFU. ■Supplemental logic and interconnect cell (SLIC) provides 3-statable buffers, up to 10-bit decoder,and PAL'like AND-OR-INVERT (AOI) in each programmable logic cell (PLC). ■Abundant hierarchical routing resources based on routing two data nibbles and two control lines per set provide ftor faster place and route implementations and less routing delay. ■Indivldually programmable drive capabillty: 12 mA sink/6 mA source or 6 mA sink/3 mA source. ■Buit-In boundary scan (IEEE↑1149.1 JTAG) and testability function to 3-state all /O pins. ■Enhanced system clock routing for low-skew. high-speed clocks originating on-chip or at any /O. ■Up to four ExpressCLK inputs allow extremely tast clocking of signals on- and off-chip plus access to internal general clock routing. ■StopCLK feature to glitchlessly stop/start the ExpressCLKs independently by user command.

Features