Microchip PL123-05NSI

Fanout Buffer (распределение)11:5

Overview

The PL123-05/-09 (-05H/-09H for High Drive) are high performance, low skew, low jitter zero delay buffers designed to distribute high speed clocks. They have one (PL123-05) or two (PL123-09) low-skew output banks, of 4 outputs each, that are synchronized with the input. The PL123-09 allows control of the banks of outputs by using the S1 and S2 inputs as shown in the Selector Definition table on page 2 of the datasheet.The synchronization is established via CLKOUT feed back to the input of the PLL. Since the skew between the input and output is less than ±100ps, the device acts as a zero delay buffer. The input output propagation delay can be advanced or delayed by adjusting the load on the CLKOUT pin.These parts are not intended for 5V input-tolerant applications.

Features

Applications

• Synchronous digital system
• Car
• Aviation
• Medical instruments
• Furniture
• Machine made
• Clock signal duplication
• Clock signal format conversion
• Clock signal level shifting
• High performance communication system