Microchip SY89871UMG

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Overview

The SY89871UMG is a 2.5V/3.3VLVPECL output precision clock divider capable of accepting a high-speeddifferential clock input (AC or DC-coupled) CML, LVPECL, HSTL or LVDS clockinput signal and dividing down the frequency using a programmable divider ratioto create a frequency locked lower speed version of the input clock (BankB).Available divider ratios are 2, 4, 8 and 16. In a typical 622MHz clocksystem this would provide availability of 311MHz, 155MHz, 77MHz, or 38MHzauxiliary clock components.The differential input buffer has a unique internal termination designthat allows access to the termination network through a VT pin. Thisfeature allows the device to easily interface to different logic standards. AVREF-AC reference is included for AC-coupled applications.The SY89871Uincludes two phase-matched output banks. Bank A (QA) is a frequency-matchedcopy of the input. Bank B (QB0, QB1) is a divided down output of the inputfrequency. Bank A and Bank B maintain a matched delay independent of the dividersetting.

Features

Applications

• Clock signal format conversion
• Clock signal level shifting
• High performance communication system
• Data center
• Cloud computing
• Network
• High speed industry
• High-end consumer electronics
• Data communication
• Telecommunications