ON PCA9654EDR2G

8I²CPOR1,65 В ~ 5,5 В-55°C ~ 125°C

Overview

The PCA9654EDR2G provides 8 bits of General Purpose parallelInput/Output (GPIO) expansion for I2C−bus/SMBus applications.The PCA9654EDR2G consists of 8−bit Configuration (Input or Output selection); Input, Output and Polarity Inversion (active HIGH or active LOW operation) registers. The system master may set the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for each Input or Output is kept in the corresponding Input or Output register. The polarity of the read register can be inverted with the Polarity Inversion register. All registers can be read by the system master.The PCA9654EDR2G open−drain interrupt (INTb) output is activated when any input state differs from its corresponding input port register state and is used to indicate to the system master that an input state has changed. The power−on reset sets the registers to their default values and initializes the device state machine.Three hardware pins (AD0, AD1, AD2) vary the fixed I2C bus address and allow up to 64 devices to share the same I2C−bus/SMBus.

Features

Applications

• Multiprotocol RFID Readers: EPC-GEN2, ISD and IPX
• IDEN, PHS, GSM Basestations
• Repeaters, Radio Links, and Modems
• Wireless Telemetry
• JTRS
• 802.11x Receivers
• IDEN
• PHS
• TD-SCDMA
• CDMA2000