Renesas 54FCT574CTLB

86,2 нс при 50 пФ4,5 В ~ 5,5 В

Overview

The 54FCT574CTDB is a low jitter, low-skew, high performance PLL-based zero delay buffer for high speed applications. Based on IDT's proprietary low jitter Phase Locked Loop (PLL) techniques, the device provides four low skew outputs at speeds up to 160 MHz at 3.3 V. When one of the outputs is connected directly to FBIN, the rising edge of each output is aligned with the rising edge of the input clock. External delay elements connected in the feedback loops will cause the outputs to occur before the inputs by the amount of propagation delay of the external element.

Features

Applications

• Data storage
• Data transfer
• Latch
• Registers
• Memory
• Frequency division
• Memory
• Event Detectors
• Data Synchronizers
• Asynchronous counter