Renesas 82V2042EPFG

Блок линейного интерфейса (LIU)LIU3,13 В ~ 3,47 В

Overview

The IDT82V2042EPFG can be configured as a dual channel T1, E1 or J1 LineInterface Unit. The IDT82V2042EPFG performs clock/data recovery, AMI/B8ZS/HDB3 line decoding and detects and reports the LOS conditions. Anintegrated Adaptive Equalizer is available to increase the receive sensitivityand enable programming of LOS levels. In transmit path, there is an AMI/B8ZS/HDB3 encoder and Waveform Shaper. There is one Jitter Attenuator,which can be placed in either the receive path or the transmit path. The JitterAttenuator can also be disabled. The IDT82V2042EPFG supports both Single Rail and Dual Rail system interfaces. To facilitate the network maintenance,a PRBS/QRSS generation/detection circuit is integrated in the chip, and differenttypes of loopbacks can be set according to the applications. Four differentkinds of line terminating impedance, 75 Ω,100 Ω, 110 Ω and 120 Ωare selectable on a per channel basis. The chip also provides driver shortcircuitprotection and internal protection diode and supports JTAG boundary scanning. The chip can be controlled by either software or hardware.The IDT82V2042EPFG can be used in LAN, WAN, Routers, Wireless BaseStations, IADs, IMAs, IMAPs, Gateways, Frame Relay Access Devices,CSU/DSU equipment, etc.

Features

Applications

• LAN Routers
• Digital Modems
• SONET/SDH terminal
• Add/Drop multiplexers (ADMs)
• T1/E1/J1 add/drop multiplexers (MUX)
• Channel Service Units (CSUs): T1/E1/J1
• Fractional T1/E1/J1
• BITS Timing
• Digital Access Cross-connect System (DACs)
• Digital Cross-connect Systems (DCS)