Renesas 9DB102BGLF

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Overview

The 9DB102BGLF zero-delay buffer supports PCI Express clocking requirements. The 9DB102BGLF is driven by a differential SRC output pair from an IDT CK409/CK410-compliant main clock generator such as the 952601 or 954101. It attenuates jitter on the input clock and has a selectable PLL Band Width to maximize performance in systems with or without Spread- Spectrum clocking.

Features

Applications

• Routers
• Ethernet switch/router
• PCI Express 2.0/3.0
• Broadcast video/audio timing
• Processor and FPGA clocking
• Any-frequency clock conversion
• MSAN/DSLAM/PON
• Fibre Channel, SAN
• Telecom line cards
• 1 GbE and 10 GbE