Renesas 9DB106BFILF

Да

Overview

The 9DB106BFILF zero-delay buffer supports PCIe Gen1 and Gen2 clocking requirements. The 9DB106BFILF is driven by a differential SRC output pair from an IDT CK410/CK505-compliant main clock generator. It attenuates jitter on the input clock and has a selectable PLL bandwidth to maximize performance in systems with or without Spread-Spectrum clocking. An SMBus interface allows control of the PLL bandwidth and bypass options, while 2 clock request (CLKREQ#) pins make the 9DB106BFILF suitable for Express Card applications.

Features

Applications

• Wireless Access Point
• Routers
• Ethernet switch/router
• PCI Express 2.0/3.0
• Broadcast video/audio timing
• Processor and FPGA clocking
• Any-frequency clock conversion
• MSAN/DSLAM/PON
• Fibre Channel, SAN
• Telecom line cards