Infineon MB90F548GSPFR-G

F²MC-16LX16 МГц128 КБ (128К x 8)

Overview

The MB90F548GSPFR-G with FULL-CAN*1 and FLASH ROM is specially designed for automotive and industrial applications. Its main features are two on board CAN Interfaces (one for MB90V545 series) , which conform to V2.0 Part A and Part B, supporting very flexible message buffer scheme and so offering more functions than a normal full CAN approach. The instruction set by F2MC-16LX CPU core inherits an AT architecture of the F2MC*2 family with additional instruction sets for high-level languages, extended addressing mode, enhanced multiplication/division instructions, and enhanced bit manipulation instructions.

• Clock    Embedded PLL clock multiplication circuit    Operating clock (PLL clock) can be selected from : divided-by-2 of oscillation or one to four times the oscillation    Minimum instruction execution time : 62.5 ns (operation at oscillation of 4 MHz, four times the oscillation clock)    Subsystem Clock : 32 kHz• Instruction set to optimize controller applications    Rich data types (bit, byte, word, long word)    Rich addressing mode (23 types)    Enhanced signed multiplication/division instruction and RETI instruction functions    Enhanced precision calculation realized by the 32-bit accumulator• Instruction set designed for high level language (C language) and multi-task operations    Adoption of system stack pointer    Enhanced pointer indirect instructions    Barrel shift instructions• Program patch function (for two address pointers)• Enhanced execution speed : 4-byte Instruction queue• Enhanced interrupt function : 8 levels, 34 factors• Automatic data transmission function independent of CPU operation    Extended intelligent I/O service function (EI2OS)• Embedded ROM size and types    Mask ROM : 256 Kbytes / 64 Kbytes / 128 Kbytes    Flash ROM : 128 Kbytes/256 Kbytes    Embedded RAM size : 2 Kbytes/4 Kbytes/6 Kbytes/8 Kbytes (evaluation chip)• Flash ROM    Supports automatic programming, Embedded Algorithm TM*    Write/Erase/Erase-Suspend/Resume commands    A flag indicating completion of the algorithm    Hard-wired reset vector available in order to point to a fixed boot sector in Flash Memory    Erase can be performed on each block    Block protection with external programming voltage• Low-power consumption (stand-by) mode    Sleep mode (mode in which CPU operating clock is stopped)    Stop mode (mode in which oscillation is stopped)    CPU intermittent operation mode    Clock mode    Hardware stand-by mode• Process    0.5 µm CMOS technology• I/O port    General-purpose I/O ports : 81 ports• Timer    Watchdog timer : 1 channel    8/16-bit PPG timer : 8/16-bit × 4 channels    16-bit re-load timer : 2 channels• 16-bit I/O timer    16-bit free-run timer : 1 channel    Input capture : 8 channels    Output compare : 4 channels• Extended I/O serial interface : 1 channel• UART 0    With full-duplex double buffer (8-bit length)    Clock asynchronized or clock synchronized (with start/stop bit) transmission can be selectively used.

Features

Applications

• Robots
• Radio
• Television
• Heater/Fan
• Calculator
• Kindle
• Christmas lights
• 3D printers
• Washing machine
• Microwave ovens