NXP HEF4040BT/S400118

Overview

The HEF4040BT is a 12-stage binary ripple counter with buffered outputs. The counter includes a clock input (CP), an overriding asynchronous master reset input (MR), and twelve fully buffered outputs (Q0 to Q11). The counter progresses when there is a HIGH-to-LOW transition on CP. Applying a HIGH level to MR clears all counter stages and sets all outputs LOW, regardless of CP. Each counter stage consists of a static toggle flip-flop. HEF4040BT can count up to 12 binary bits and is designed for various digital counting and frequency division applications.

Available in a 16-pin SOIC (Small Outline Integrated Circuit) package

Features