NXP MPC8572EPXARLD

PowerPC e5001,067 ГГцDDR2, DDR310/100/1000 Мбит/с (4)0°C ~ 105°C

Overview

NXP’s next-generation PowerQUICC® III integrated communications processors are designed to provide solutions for symmetrical and asymmetrical multi-core systems. Based on the scalable e500 processor and system-on-chip (SoC) platform, they deliver dual-core gigahertz plus processing performance with advanced content processing and security features.

Support for high-speed interfaces on the MPC8572EPXARLD enables scalable connectivity to network processors and/or ASICs in the data plane while the MPC8572EPXARLD platform handles complex, computationally demanding control plane processing tasks. These processors include dual memory controllers supporting DDR2 and DDR3 for future proofing and error correction codes for high reliability, enhanced Gigabit Ethernet (GbE) support and double precision floating point.

Features

The following list provides an overview of the MPC8572E feature set:

Two high-performance 32-bit Book E-enhanced cores that implement the Power Architecture technology:

Each core is identical to the core within the MPC8548 processor.

32-Kbvte L1 instruction cache and 32-Kbyte L1 data cache with parity protection. Caches can be locked entirely or on a per-line basis, with separate locking for instructions and data.

Signal-processing engine(SPE)APU(auxiliary processing unit). Provides an extensive

instruction set for vector (64-bit) integer and

fractional operations.These instructions use both

Applications

Air Conditioning

Motor Drives

Servo Drives

UPS Systems