NXP PCA9617ATPZ

Буфер, ReDriver2-проводная шина2-проводная шина1 МГц1

Overview

The is a CMOS integrated circuit that provides level shifting between low voltage 5.5 V) and higher voltage 5.5 V) Fast-mode Plus (Fm+) I2C-bus or SMBus applications. While retaining all the operating modes and features of the I2C-bus system during the level shifts, it also permits extension of the I2C-bus by providing bidirectional buffering for both the data (SDA) and the clock (SCL) lines, thus enabling two buses at 1 MHz pF at lower speeds. Using the PCA9617ATPZ enables the system designer to isolate two halves of a bus for both voltage and capacitance. The SDA and SCL pins are overvoltage tolerant and are high-impedance when the PCA9617ATPZ is unpowered. The 5.5 V bus port B drivers have the static level offset, while the adjustable voltage bus port A drivers eliminate the static offset voltage. This results in a LOW on the port B translating into a nearly 0 V LOW on the port A which accommodates the smaller voltage swings of lower voltage logic. The static offset design of the port B PCA9617ATPZ I/O drivers prevents them from being connected to the static or incremented offset of other bus buffers. Port A of two or more PCA9617As can be connected together, however, to allow a star topography with port A on the common bus, and port A can be connected directly to any other buffer with static or incremented offset outputs. Multiple PCA9617As can be connected in series, port A to port B, with no build-up in offset voltage with only time of flight delays to consider. The PCA9617ATPZ drivers are not enabled unless VCC(A) is above 0.8 V and VCC(B) is above 2.2 V. The EN pin is referenced to VCC(B) and can also be used to turn the drivers on and off under system control. Caution should be observed to only change the state of the enable pin when the bus is idle. The output pull-down on the port B internal buffer LOW is set for approximately 0.55 V, while the input threshold of the internal buffer is set about 90 mV lower (0.45 V). When the port B I/O is driven LOW internally, the LOW is not recognized as a LOW by the input. This prevents a latching condition from occurring. The output pull-down on port A drives a hard LOW and the input level is set 0.35VCC(A) to accommodate the need for a lower LOW level in systems where the low voltage side supply voltage is as low 0.8 V.

Table 2. Ordering options Orderable part number PCA9617ADPJ PCA9617ATPZ Package Packing method Minimum order quantity 2500 4000 Temperature range Type number

Features

Applications

• PECL-to-LVDS Translation
• Cellular Phone Base Stations
• Add/Drop Muxes
• Digital Crossconnects
• Network Switches/Routers
• Backplane Interconnect
• Clock Distribution
• Protection Switching
• Loopback
• Clock Distribution