TI XIO1100ZWSR

TI-PIPE1,35В ~ 1,65В, 3В ~ 3,6ВПоверхностный монтаж

Overview

The XIO1100ZGB is a PCI Express. PHY that is compliant with PCI Express Base Specification Revision 1.1 and that interfaces the PCI Express Media Access Layer (MAC) to a PCI Express serial link by using a modified version of the interface described in PHY Interface for the PCI Express. Architecture (also known as PIPE interface) by Intel Corporation. This modified version of the PIPE interface is referred to as a TI-PIPE interface throughout this data manual.

In addition to the TI-PIPE interface, the XIO1100ZGB has some TI-proprietary side-band signals that some customers may wish to use to take advantage of additional XIO1100ZGB low-power state features (for example, disabling the PLL during the L1 power state).

Features